"Pixel-level sampling CMOS Vertex Detectors for ILC"

Our Pixel Vertex Detector R&D Effort for ILC is an outgrowth of a pixel upgrade effort for the Belle detector at the KEK B Factory. For this further development we are joined by Fermilab, and consist of groups from Europe, Japan and the US. Any readout architecture capable of surviving the much harsher and lower track momentum requirement of a Super KEKB environment, should be a viable alternative for an ILC Pixel Vertex Detector. Given the near-term nature of this development, it provides the possibility to evolve and test a full detector system under actual running conditions at the world's highest luminosity collider.

Deep submicron CMOS shows great promise for ILC vertexing through the implementation of complex algorithms to reduce occupancy. We intend to explore these possibilities, with the current 3 generations of experience in such technologies to guide our effort.

To date we have made good progress in addressing some of the key issues needed before a CMOS (MAPS) type of detector may be used in the ILC environment:

Much work remains to be done:

Please address the following questions in your statement.

This topic: ILC/WWS > WebHome > Instructions > CreateProjectPage > VtxHawaiiSampling > VtxHawaiiSamplingStatement
Topic revision: 12 Nov 2005, DanPeterson
This site is powered by FoswikiCopyright © by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding CLASSE Wiki? Send feedback