CBPM_TIM address space							from 1/18/09 document
							converted to digital: 5/29/2014
							
The CBPM DSP is described here: /nfs/acc/user/cesrdaq/hardware/BPM/6048-113_DSP_Board/Docs/DSP_Board_Programming_V5-13.doc 							
"In the section called ""Timing Board"" it describes the registers on the Timing Board"							
DSP Offset for timing board:			0x10020000				
							
addr offset	data range	unit	function				
0x00	0 -> 1023	10pS	block A global delay 1				
0x01	0 -> 1023	10pS	block A global delay 0				
0x02	0 -> 1023	10pS	ADC_clk3 delay				
0x03	0 -> 1023	10pS	ADC_clk2 delay				
0x04	0 -> 1023	10pS	ADC_clk1 delay				
0x05	0 -> 1023	10pS	ADC_clk0 delay				
							
0x08	0 -> 1023	10pS	block B global delay 1				
0x09	0 -> 1023	10pS	block B global delay 0				
0x0A	0 -> 1023	10pS	ADC_clk7 delay				
0x0B	0 -> 1023	10pS	ADC_clk6 delay				
0x0C	0 -> 1023	10pS	ADC_clk5 delay				
0X0D	0 -> 1023	10pS	ADC_clk4 delay				
							
0x10	0 -> 9	2nS	block A turns marker delay				
0x11	0 -> 62	N	block A clock freq. f = 500MHZ/(64 - N)				
0x12	0 -> 3	M	block A clock width w = 2nS * 2**M				
							
0x18	0 -> 9	2nS	block B turns marker delay				
0x19	0 -> 62	N	block B clock freq. f = 500MHZ/(64 - N)				
0x1A	0 -> 3	M	block B clock width w = 2nS * 2**M				
							
0x1F	0 -> 60	42nS	Common Turns Marker Delay