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"SOI and 3D Detector Geometries"


  • What are the goals of this R&D project. How does this R&D project address the needs of one or more of the detector concepts?

The object of this work is to develop and demonstrate a pixel detector based on three-dimensional integration of sensor and readout electronics. Development of this technology will allow production of pixel sensors which are thin (<50 microns), have excellent and well controlled charge collection using fully depleted devices, and can use full CMOS readout without parasitic charge collection. These detectors will also be radiation hard. Such a device can be used as part of the vertex or forward detector for any of the detector concepts. Two approaches are being examined, Silicon on Insulator (SOI) technology and three dimensional integration.

SOI is based on a thin “device wafer” with CMOS circuitry processed on a thicker “handle wafer”, which is normally passive. In this work we will explore using a high resitivity handle wafer as a detector with vias between the device and detector layers. The detector diode is formed in the handle wafer as part of the topside processing.

A second approach which we will study is “three dimensional” integration of CMOS readout and detector wafers. This approach is similar to SOI, but the CMOS and detector wafers are processed independently, thinned, and then bonded. Bonding can be done using known good readout die bonded to a sensor wafer. Vias are then etched and filled to connect the CMOS and detector layers.

The object of this work is to develop and demonstrate a pixel detector based on three-dimensional integration of sensor and readout electronics. Development of this technology will allow production of pixel sensors which are thin (<50 microns), have excellent and well controlled charge collection using fully depleted devices, and can use full CMOS readout without parasitic charge collection. These detectors will also be radiation hard. Such a device can be used as part of the vertex or forward detector for any of the detector concepts. Two approaches are being examined, Silicon on Insulator (SOI) technology and three dimensional integration.

SOI is based on a thin “device wafer” with CMOS circuitry processed on a thicker “handle wafer”, which is normally passive. In this work we will explore using a high resitivity handle wafer as a detector with vias between the device and detector layers. The detector diode is formed in the handle wafer as part of the topside processing.

A second approach which we will study is “three dimensional” integration of CMOS readout and detector wafers. This approach is similar to SOI, but the CMOS and detector wafers are processed independently, thinned, and then bonded. Bonding can be done using known good readout die bonded to a sensor wafer. Vias are then etched and filled to connect the CMOS and detector layers.

  • If there are multiple institutions participating in this project, please describe the distribution of responsibilities.

Fermilab will provide support for CMOS design and testing, radiation testing, and test beam and laser test work. For the SOI work American Semiconductor will provide device design and modeling, define process flow, and manage device fabrication. Purdue will provide support for device testing and detector layer design.

  • Are there significant recent results?

No, this project is just beginning.

  • What are the plans for the near future(about 1 year)? What are the plans on a time scale of 2 to 3 years?

The initial phase (~1 year) of the SOI work will concentrate on the type (float zone, epitaxial, or Cz material) and model the processing, of the handle wafer, including wafer thinning and backside contact fabrication. We will also irradiate samples of FLEXFET SOI transistors. CMOS processing will be in 0.18 or 0.13 micron technology. If successful this will be followed in phase II (2-3 years) by a ~9 mm square pixel device with test structures and prototype pixel readout. This phase will require full custom processing of a batch of 200 mm SOI wafers. This will allow radiation tests, device thinning, and charge collection studies. We are submitting a DOE STTR grant for this work with American Semiconductor Inc. Our collaboration with American Semiconductor gives us access to a state-of-the-art IC line with the ability to specify the details of the process flow.

The initial phase (~1 year) of the 3D work will use BTeV readout and detector wafers to explore bonding and interconnect technology. We will choose an interconnect technology, measure yields, and test the quality of the detector wafer after processing. If the first phase is successful, the second phase (2-3 years) would use an ILC-specific sensors and readout using standard 0.25 or 0.13 micron CMOS designed specifically for the ILC. This will require design and fabrication of both the detector and readout wafers. The readout wafers could be part of a multiproject submission

  • Are there critical items that must be addressed before significant results can be obtained from this project?

The effects of charges in the oxide or adhesive which separate the readout and detector layers in the SOI and 3D devices need to be understood. A choice of substrate which is compatible with the SOI process and which can be thinned with a backside contact provided will be a focus of the phase I SOI work and should also address similar issues for the 3D device.

  • Is the support for this project sufficient? Are there significant improvements that could be made with additional support?

The support for the SOI part of this project will be sufficient if the American Semiconductor STTR proposal is approved. Additional support as listed in the ("prioritization") form will be needed to implement phase II of the 3D work.


Please address the following questions in your statement.

  • What are the goals of this R&D project. How does this R&D project address the needs of one or more of the detector concepts?

  • If there are multiple institutions participating in this project, please describe the distribution of responsibilities.

  • Are there significant recent results?

  • What are the plans for the near future(about 1 year)? What are the plans on a time scale of 2 to 3 years?

  • Are there critical items that must be addressed before significant results can be obtained from this project?

  • Is the support for this project sufficient? Are there significant improvements that could be made with additional support?