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"Pixel-level sampling CMOS Vertex Detectors for ILC"

Our Pixel Vertex Detector R&D Effort for ILC is an outgrowth of a pixel upgrade effort for the Belle detector at the KEK B Factory. For this further development we are joined by Fermilab, and consist of groups from Europe, Japan and the US. Any readout architecture capable of surviving the much harsher and lower track momentum requirement of a Super KEKB environment, should be a viable alternative for an ILC Pixel Vertex Detector. Given the near-term nature of this development, it provides the possibility to evolve and test a full detector system under actual running conditions at the world's highest luminosity collider.

Deep submicron CMOS shows great promise for ILC vertexing through the implementation of complex algorithms to reduce occupancy. We intend to explore these possibilities, with the current 3 generations of experience in such technologies to guide our effort.

To date we have made good progress in addressing some of the key issues needed before a CMOS (MAPS) type of detector may be used in the ILC environment:

  • Signal processing/SNR
  • Radiation hardness
  • Mechanical support/cooling of thin devices
  • Readout speed/functionality

Much work remains to be done:
  • Thinning/active edges
  • EMI impact on pixel storage and readout

Please address the following questions in your statement.

  • What are the goals of this R&D project. How does this R&D project address the needs of one or more of the detector concepts?

  • If there are multiple institutions participating in this project, please describe the distribution of responsibilities.

  • Are there significant recent results?

  • What are the plans for the near future(about 1 year)? What are the plans on a time scale of 2 to 3 years?

  • Are there critical items that must be addressed before significant results can be obtained from this project?

  • Is the support for this project sufficient? Are there significant improvements that could be made with additional support?