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"Vertex Detector R&D for Future High Energy Linear e+e- Colliders"

The Pixel Vertex Detector R&D project of the Oregon-Yale group is aimed at developing a vertex detector sensor for the ILC that satisfies the physics and machine requirements for vertexing. The time structure of the ILC necessitates an extremely fast sensor for the vertex detector elements. This effort, therefore, has started on the development of monolithic CMOS pixel detectors that allow extremely fast, non-sequential readout of only pixels containining hits. This feature significantly decreases the readout time required from a device that reads out all pixels, such as a CCD.

Another important possibility for these CMOS detectors is the time stamping of hits with single bunch crossing precision. This significantly reduces the effective backgrounds.

During 2004-5, in collaboration with SARNOFF, Inc. (RCA’s silicon fabrication house) with whom we had an R&D contract, we developed a draft conceptual design for a device. Each chip consists of two particle detection layers, one consisting of an array of 50μ x 50μ pixels (Macro Pixel Array) and one consisting of an array of 5μ x 5μ pixels (Micro Pixel Array) Each pixel of the Macro Pixel Array detects up to four hits in an ILC bunchtrain (~ 1 msec) and records the time of the hits to a precision better than the inter-bunch spacing. The Micro Pixel Array records hits in the x-y array with 3 bit pulse height resolution within each pixel.

The project is now ready to move on to detailed design, which will start in 2005-6.

Issues to be addressed during the detailed design phase include:

• Achieving all the design features simultaneously on one chip

• Thinning of the devices

• Radiation hardness

• Power consumption

• Impact of electromagnetic interference on the functioning of the device at the pixel level