Cornell University Unit Name

"Hybrid pixel detector R&D"

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Over the last ten years, a number of groups worldwide have invested a large amount of effort in a successful program to develop hybrid silicon pixel detectors. The current generation of detectors combines radiation tolerant n-in-n silicon pixel sensors with high speed, radiation tolerant, CMOS readout electronics. These devices provide extraordinary pattern recognition power and near 100% efficiency. The spatial resolution that can be achieved depends on the area required for readout electronics, which in turn depends primarily on the readout speed that is required. BTeV beam tests demonstrated that spatial resolution (in the narrow pixel dimension) better than 10 microns is possible for all incident track angles given 50 micron x 400 micron pixels and a sensor thickness of 300 microns.

In a hybrid pixel detector, the sensor and readout chip are bump bonded to one another using a process that does not change any of the electrical properties of either the sensor or the readout chip. This means that the sensor and the readout chip can be developed separately and can be optimized separately. The current generation of detectors has been optimized for use at high luminosity hadron collider experiments. These detectors are not attractive candidates for use at the ILC because the total amount of material is typically ~2% of a radiation length per measurement.

The object of this effort is to explore the possibility of greatly reducing the amount of material in a hybrid silicon pixel detector while still retaining near 100% efficiency, excellent time resolution, and high-speed, zero-suppressed readout. To this end, two questions will be addressed:

1. How far can the readout chips be thinned without making flip-chip assembly problematic?

2. Can the cooling requirements of the readout chip be reduced to the point that gas cooling of the hybrids is sufficient?

In FY06, existing prototype BTeV pixel readout chips will be thinned and bump-bonded to prototype BTeV pixel sensors. The ALICE pixel detector uses readout chips that are thinned to 150 microns. Our initial goal is to demonstrate proper detector operation with BTeV readout chips thinned to 80 microns thickness. If additional funds are available in FY06, we will purchase additional BTeV-style pixel sensors fabricated using silicon wafers thinner than our existing 270 micron thick prototypes.

The ILC is expected to operate with “trains” of beam bunches approximately 1 millisecond long, separated by 199 milliseconds. If the pixel readout chips do not require power for most of the 199 milliseconds between bunch crossings, then the heat generated by the readout chips will be greatly reduced. During FY06, we will use existing prototype BTeV readout chips to explore the extent to which cooling requirements can be reduced by power management. Alternative readout chip designs may also be considered and simulated.

If the results obtained in FY06 are promising, then in FY07 a new readout chip will be designed. This chip will be a modification of the BTeV design optimized for low power consumption. Depending on the availability of funds we will either fabricate a full sized version of the new chip, or we will fabricate a smaller readout chip as part of a multi-project wafer submission. An engineering run of a full sized chip will provide many wafers that can be thinned and bump bonded to sensors. If a smaller device is fabricated as part of a multi-project wafer submission, we will measure the performance and power consumption of bare chips (not bump bonded to sensors).

Depending on the progress made in earlier years, hybrids will be constructed and tested in FY08 using thin sensors and low power readout chips.

Either in FY07 or FY08, the status of this R&D effort will be assessed. If the results are sufficiently promising, further plans will be made to develop ultra-thin hybrid pixel detectors. If not, the experience gained in thinning readout chips and bump-bonding ultra-thin chips to sensors will be invaluable experience for the various monolithic pixel projects and for the mechanical design of future vertex detectors.

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Please address the following questions in your statement.

• What are the goals of this R&D project. How does this R&D project address the needs of one or more of the detector concepts?

• If there are multiple institutions participating in this project, please describe the distribution of responsibilities.

• Are there significant recent results?

• What are the plans for the near future(about 1 year)? What are the plans on a time scale of 2 to 3 years?

• Are there critical items that must be addressed before significant results can be obtained from this project?

• Is the support for this project sufficient? Are there significant improvements that could be made with additional support?