BPM6W1 Electronic Logbook 2005

26 Dec 2024 - 14:05

Hardware Layout

• Diagram of hardware layout:
  
• This diagram in pdf format: bpm_bsm_flm_PAC_diagram.pdf

April 2005

April 29, 2005 (E.Tanke, C.Strohman, J.Dobbins): Start of BPM II testing

• BPM II testing has started in lab 215.

-- EugeneTanke - 29 Apr 2005

May 2005

May 10, 2005 (E.Tanke): Test program for BPM

• [CESR.PALMER.TS101.TEST_BPM]get_tim is a timing scan program which requires no program in the DSP

-- EugeneTanke - 10 May 2005

June 2005

June 15, 2005 (E.Tanke): Timing scan program for BPM

• A timing scan program for BPM has been written and tested:
  • [CESR.PALMER.TS101.TEST_BPM]get_bpmtime

-- EugeneTanke - 15 Jun 2005

July 2005

July 11, 2005 (N. Taylor, E.Tanke): Testing of clock register settings

• A program for testing of clock register settings has been written:
  • [CESR.PALMER.TS101.TEST_BPM]get_bpmclock

-- EugeneTanke - 11 Jul 2005

July 13, 2005 (E.Tanke): Measurement with one button of CESR BPM 6WA

• A measurement with one button of CESR BPM 6WA was made using the new BPM DAQ hardware; gain was set to 8, clock register was set to 79.
  • BPM6WA.pdf contains a plot of the 9x5 positrons and 7x5 electrons observed. Horizontal axis is bunch number (1..183) and vertical axis is ADC counts.

July 28, 2005 (N.Taylor, E.Tanke): Investigation of clock settings with BPM DSP in R101

• Programs were written to assist in finding the best clock setting for the new BPM DAQ hardware. The controls program GET_BPMCLOCK works in conjunction with the DSP program TEST_BPMCLOCK for this purpose. After an elimination process of different clock settings for CESR BPM 6WA , 5 clock settings were retained to do statistical checks on. The results shown in clock_settings.pdf were obtained for 1 million turns and a gain of 8 on all channels. A threshold of 500 was used (i.e. if the ADC count acquired was more than 500 away from the pedestal, this acquisition would be considered a bad one). The global timings used were A=B=1050, corresponding to the peak for both electrons and positrons at CESR BPM 6WA. The card timings have, for the moment, been fixed at 700 in the GET_BPMCLOCK program.
• The results indicate the best clock setting out of the 5 chosen, but also seem to indicate that the different channels on the different boards have sizeable differences in error count: channel 1 of ADC board SN3 gave 0 errors through all the tests, channel 1 of SN2 gave 24.

August 2005

August 3, 2005 (E.Tanke): Investigation of clock settings with BPM DSP in R101 (bis)

• Tried clock settings for threshold=2000 (the RMS noise level is ~38 ADC counts) but spurious data still occured on all channels for 2 M turns.
• In the ~tanke/cesr_home/ts101V4/test_bpmclock directory is a modified version of TEST_BPMCLOCK: it now stores the clock#, channel#, bunch#, turn# and ADC count for any spurious data encountered. Also modified the GET_BPMCLOCK fortran code to read these data and write them to a file ( clock_details.dat ). Data in there are in the order as described above. The fortran code was also modified to print out the sum of spurious dat encountered for each clock setting in the clock_output.dat file.
• Current position-card-(channels) map: 1-SN5-(0,1) ; 2-SN4-(2,3) ; 3-SN2-(4,5) ; 4-SN3-(6,7)
• Ran the test programs for a couple of iterations on all channels, TH=2000, global Ta=Tb=1050 :
  • #1: 10 turns -----> Bad clocks: 32-47, 96-111 (bad for all channels except channel 7)
  • #2: 100 turns ----> Bad clocks: 64,68,72,76,80,84,88,92,112,116,120,124 (essentially channel 4)
  • #3: 1000 turns ---> Bad clocks: 65,66,81,82,113,114 (essentially channel 5)
  • #4: 10000 turns --> Bad clocks: 7,51,71 (essentially channel 7)
  • #5: 100000 turns -> 19 Bad clocks (see table below). Bunch 182 seems to occur often. Rerun without the bad clocks of channel 7 (see next iteration)

clock	channel	bunch	ADC count
5	6	182	-9848
8	1	182	-26228
8	5	182	-30444
9	6	182	-30480
16	6	182	-32724
24	6	182	-30716
24	5	182	-8208
26	1	182	-8220
29	1	182	-16416
48	7	167	28796
48	6	182	-2044
48	5	182	-8196
50	7	31	-2184
50	5	182	-20180
52	1	182	30668
55	5	182	-8240
58	3	182	2320
77	6	182	-3884
78	6	182	-32768
83	6	182	-2372
90	6	182	-2044
93	1	182	-26360
94	6	182	-8200
115	7	47	3828

August 4, 2005 (E.Tanke, M.Taylor): Investigation of clock settings with BPM DSP in R101 (bis)

• Continuation of yesterday's tests:
  • #6: 200000 turns -> Results are in table below; again bunch 182 seems to occur often.

clock	channel	bunch	turn	ADC count
1	1	182	88784	-18024
1	4	182	100240	-2132
2	5	182	48688	-10792
2	6	182	134608	-11032
4	4	182	51552	-3956
4	5	182	97376	12312
5	6	182	40096	-8276
6	1	182	111696	6416
13	6	182	68736	-2312
15	4	182	183296	-30312
16	6	182	114560	-30512
17	3	182	163248	-30464
20	3	182	146064	-26360
20	6	182	148928	-9744
21	3	182	54416	-6960
21	5	182	54416	20732
21	1	182	97376	-18152
23	5	182	183296	-20432
24	1	182	143200	-26368
24	3	182	143200	-30460
26	6	182	57280	-8252
27	5	182	40096	-8228
27	6	182	117424	-11020
28	0	182	163248	-24772
49	7	103	26848	31972
49	7	119	59264	-3984
49	7	146	65059	29816
53	6	182	45824	-11048
54	6	182	100240	16448
54	6	182	189024	-32756
55	5	182	140336	4208
56	3	182	177568	-24824
57	1	182	63008	26460
61	6	182	68736	21604
62	6	182	57280	-30468
67	5	56	146282	-2892
67	5	98	180973	-2944
69	5	182	11456	-18148
70	1	182	63008	30584
70	5	182	63008	-11020
70	6	182	166112	-30716
74	3	182	140336	17452
75	6	182	40096	-9764
75	5	182	45824	-10764
77	5	182	191888	-16620
78	6	182	65872	-30548
78	6	182	120288	-30708
79	1	182	37232	26420
79	6	182	74464	-11080
83	6	182	80192	-11132
83	1	182	143200	-16428
86	6	182	148928	-30680
90	3	182	194752	-6440
94	5	182	42960	-30436
95	6	182	117424	-32768
117	3	182	2864	-24828
119	5	182	17184	20720
126	5	182	128880	12552
127	5	182	186160	12316

• Tests so far were for 'normal' arrival time of the turn marker (i.e. the TURN_MARK_DELAY register is set to 0). Setting the TURN_MARK_DELAY register to 1 (i.e. delayed arrival) was found to yield similar results.

• Modified clock testing codes to also print out the buffer address of were spurious data occur. Also included setting of card timings (before these were hardwired to 700 in the DSP code).

• So far card timings were 700 and Ta=Tb=1050.

October 2005

October 14, 2005 (E.Tanke): New serial channel for BPM in R101

• A new serial channel has been made available for testing the BPM electronics in R101. The node name is CBPM ADR TST 5, which corresponds to the grey cable with connector marked #2.

October 19, 2005 (E.Tanke): Channel mapping

• The following mapping is used: TopIn=card0,BotIn=card1,BotOut=card2,TopOut=card3

October 21, 2005 (E.Tanke): Status of BPM DSP work

• It was found that spurious results on acquisition cease to exist if one does not include data taken over the last turn of the last bunch.
• First beam position measurements have been taken at 6WA, using newly developed test programs:
  • test_bpmtime and get_bpmtime (time scan)
  • test_bpmraw and get_bpmraw (acquire raw data)
  • test_bpmnavg and get_bpmnavg (acquire averaged data)
  • process_bpm (calculate positional data from get_bpmraw and get_bpmnavg output files)

October 26, 2005 (E.Tanke): BPM raw data analysis

• Data taken with get_bpmraw on 24-Oct-2005; file stored on server under ~tanke/cesr/ts101/bpm6w/test_bpmraw/2005_10_24
• Bunches selected: 1 e- bunch, 1 e+ bunch and 1 pedestal. Timing settings: global A= global B=820, cards=700, gains=8
• Analysis made with new plotting programs: histoplot (in [cesr.palmer.ts101.plotprogs]) and bsmplotter (in [cesr.palmer.ts101.test_bpm])
• Analysis results are in bpm_raw24Oct2005.pdf
• The file bpm_gains.pdf shows 4 timing scans taken today, each with a timing stepsize of 10. Today the beams are 7x4 e- (122mA) and 9x4 e+ (170 mA). The 4 timing scans differ in gain setting. Note that a gain higher than 7 causes the position of the peak of the bunches relative to eachother to shift in time. Note that with gain 8 there is no visible saturation; saturation is visible with gain 10.

October 27, 2005 (E.Tanke): BPM raw data analysis (continued) and gain issues

• Data taken with get_bpmraw on 26-Oct-2005; file stored on server under ~tanke/cesr/ts101/bpm6w/test_bpmraw/2005_10_26
  • Bunches selected: 1 e- bunch, 1 e+ bunch and 1 pedestal. Timing settings: global A= global B=817, cards=700, gains=6
  • Analysis results are in bpm_raw26Oct2005.pdf
• Regarding gains, the BPM version of the DSP has 8 gain registers [0..7], one per channel. Although each register is 4 bit, only 3 bits are actually being used. One should only use the even gains ( i.e. 0,2,4,6,8,10,12,14). Below is a table of pedestal RMS values during beam conditions (210 mA e-, 207 mA e+ ). Pedestal data were taken halfway between T4B1 e- and T4b1 e+. At the highest gains one may start to see the effect of the filter being driven too hard.

	Gain 0	Gain 2	Gain 4	Gain 6	Gain 8	Gain 10	Gain 12	Gain 14
Channel	RMS	RMS	RMS	RMS	RMS	RMS	RMS	RMS
0	38	38	39	39	39	39	39	45
1	37	37	37	37	37	37	39	42
2	38	38	38	38	38	38	40	48
3	37	37	37	38	38	38	39	45
4	37	37	37	37	37	40	47	67
5	37	37	37	37	38	40	47	70
6	38	38	38	38	39	42	51	78
7	38	38	38	38	38	42	51	78

November 2005

November 11, 2005 (E.Tanke): BPM measurements using averaged data

• Some time jitter was found in the acquired raw data, resulting in amplitude jitter (and therefor position jitter). Causes of the timing jitter are being investigated (goal being that one wants to be able to make reliable measurements of raw data).
• A new set of codes, get_bpmlavg and test_bpmlavg, has been created to be able to read BPM data over longer periods of time. The user specifies the number of tirns to average over, the number of averages and the distance in time (time unit is turns) between averages. By taking averaged data one minimizes the effect of the above mentioned time jitter.
• Measurements have been made with test_bpmlavg; some of the results were shown at the MS_meeting_11Nov2005.pdf.
  • Over the length of the run, the electron position (both H and V) varies; this change seems to be related to beam current. The positron H&V positions do not see this change.
  • On the 15 minute time scale, (irregular) oscillations are seen on the beam position; this may in part be related to the temperature in room 101, where the DSP is located (see the second plot shown at the MS meeting). Furthermore, the synchrotron RF 85F water, which also feeds some skew quads in the IR, displays oscillations on a similar time scale.
  • Oscillations at the level of ~ 1.2 Hz are seen both for positrons and electrons. In the V plane they seem to be in phase; in the H plane they are not.

November 15, 2005 (E. Tanke): Machine study of 15-November-2005 with BPM 6W

• 06:41 First measurement with full load of e- only, taking data for 1 e- bunch, 1 pedestal and 1 (zero current) e+ bunch; measurement conditions:
  • Raw data, 140k turns, global Ta=Tb=800. Tcards(0..7)=(750,710,750,714,730,734,733,738). Data files stored on server under ~tanke/cesr/ts101/bpm6w/test_bpmraw/2005_11_15
• 07:20 With pretzel off, timing scans in order to find timings such as to yield maximum amplitude for each of the channels at the same global timing setting.
  • 07:23 Timing scans for T1B1 e+ (5 mA) only. After a series of scans find that Tcard(1,3,5,7)=(706,714,732,736) yield maximum amplitude at Tglob=804.
  • 07:42 Timing scans for T1B1 e- (5 mA) only. After a series of scans find that Tcard(0,2,4,6)=(716,727,729,740) yield maximum amplitude at Tglob=804.
• Note that on the 15 minute time scale, (irregular) oscillations are seen (see 11-Nov-2005 entry); these are thought to be caused by changes in temperature. Yesterday it was found that changes in temperature on the cards follow a similar rhythm as these oscillations and these may cause slip in timings. Once this problem is fixed, the above procedure will need to be repeated.

November 30, 2005 (E. Tanke): Temperature compensation

• BPM data from 6W are being taken and stored on the controls system under LOG3$DISK:[CESR.CESRBPM.TS101.BPM6W1]
• Every hour new data files are stored; the data files are typically ~ 57 min long (it takes ~ 3 min to transfer the data from the DSP to the control system).
• Temperature compensation has been attempted on the data obtained from the BPM at 6W using the bpm_log program under [CESR.TS101.BPM]
  • A linear regression is fitted onto each of one hours worth of data (see green lines in temp_fit_30Nov2005.pdf) to which a temperature based function (in red) is added. This temperature is the average temperature over the 4 ADC card temperatures; the amplitude is fixed such that the RMS of the "raw" position and that of the average temperature is the same. The bottom plot shows the difference between the "raw" position and the temperature based compensation; the peak to peak amplitude is about half of the "raw" data.
  • Note that if there was a beam fill during the 1 hour of measurement data, the compensation will be less accurate.
  • Currently this compensation scheme has only been tried out on H e+ positional data.

December 2005

December 2, 2005 (E. Tanke): Temperature compensation (follow up)

• The temperature compensation scheme as discussed on November 30, 2005 has now been applied to both species and both planes; see regression.pdf. Differential positions (i.e. electron-positron) are also shown in this document.

December 5, 2005 (J. Codner): Tiger SHARC Development

• Have requested that Computer Group install Analog Devices Tiger SHARC development system on PC137. Have checked with C. Strohman and Sergey Belomestnyhk and do not see any license conflicts at this time, although there are now just two network licenses. SRF group foresees the need for additional licenses in the future.

December 21, 2005 (E. Tanke, C. Strohman): BPM re-installed in R101 with ethernet card and Xilinx rev 5.

• BPM re-installed in R101 with ethernet card and Xilinx rev 5.
• Minor bug in Xilinx code corrected (sign bit of ADC counts was not properly taken into account)