Beamsize Monitor Current Monitoring and Shutter Control Upgrade
- 6 microamps per channel current limit
- 100 microamps total current limit
- Want to set both single and all channel thresholds
- After N samples of overcurrent, disable shutter
- After M additional samples of overcurrent, disable HV
- Shutter control
- Re-triggerable (shutter will open or close upon writing to shutter control register)
- "Exposure" time, during which the shutter is open, ranges from 10 turns to 65K x 10 turns; to be written to shutter control register
- HV control
- Disable HV by writing 0 to its DAC
- Store number of last channel to have caused overcurrent
- Freeze current values of all channels if HV disabled
- Status word will contain:
- Flag to indicate that HV was switched off due to overcurrent
- Flag that shutter was disabled
- Shutter status close/open using counter
How to talk to the BSM current monitor board
- Xilinx registers on the DSP board, used to talk to the BSM Current Monitor:
- CUR_MON_STAT 0X10040030 (dec=268697648)
- CUR_MON_WR_DAT 0X10040031 (dec=268697649)
- CUR_MON_WR_ADR 0X10040032 (dec=268697650)
- CUR_MON_RD_ADR 0X10040033 (dec=268697651)
- CUR_MON_RD_DAT 0X10040034 (dec=268697652)
- The current monitor board interface uses indirect addressing to access data within the current monitor chip. First, the program must read from the CUR_MON_STAT register to be sure that the serial link from the DSP board to the current monitor board is idle, and is not in a timeout error condition. A value of '0' (‘0x00000000’) indicates that the interface is ready to receive commands and/or data. A value of '1' (‘0x00000001’) indicates that the interface is busy. A value of '-32768' (‘0xffff8000’) indicates that a timeout has occurred.
- If the interface is busy, any data written to the CUR_MON_WR_DAT, CUR_MON_WR_ADR, or CUR_MON_RD_ADR registers will be ignored. Data read from the CUR_MON_RD_DAT register will be undefined.
- If a timeout has occurred, the only way to clear the error code and re-enable the interface is to write a value of ‘-1’ (0xffffffff) to the CUR_MON_STAT register. This will reset all of the logic on the DSP board side of the current monitor board interface. The timeout time is about 2.5 usec. A timeout is a serious condition that requires investigation.
- Do not confuse the CUR_MON_STAT register with the CSR register (to be described later) on the current monitor board. The CUR_MON_STAT register is solely concerned with the communications link to the current monitor board.
- To write data, the data is written to the CUR_MON_WR_DAT register. The destination address is then written to the CUR_MON_WR_ADR register. The serial transfer will then start and the BUSY bit in the CUR_MON_STAT register will be set. When the transfer is complete, the BUSY bit will be cleared.
- To read data, the destination address is written to the CUR_MON_RD_ADR register. The serial transfer will then start and the BUSY bit in the CUR_MON_STAT register will be set. When the transfer is complete, the BUSY bit will be cleared. The data can then be read from the CUR_MON_RD_DAT register.
- Any operations that write to the CUR_MON_WR_DAT, CUR_MON_WR_ADR, and CUR_MON_RD_ADR registers will be ignored if the interface is busy.
- Addresses written to the CUR_MON_WR_ADR and CUR_MON_RD_ADR registers are 8-bit. All data written to the CUR_MON_WR_DAT register will be truncated at 16-bits. All data read from the CUR_MON_RD_DAT register will be 16-bit data that is sign-extended to 32-bits.
Topic revision: r3 - 22 May 2007, EugeneTanke