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ERLBPM Electronic Logbook 2006

25 Jul 2024 - 13:10

November 2006

November 27, 2006 (E. Tanke): ERL BPM status

  • Front-end filters were added to the 4 ADC boards last week
  • All 8 ADC channels have undergone basic signal testing
  • A frequency scan versus ADC amplitude for channel 2 has been made (see below). Note that the wave generator used (a Wavetek Model 90) only goes up to 20 MHz and needs re-calibration (by setting the generator to 11 MHz one obtains only 10 MHz); the fitted frequencies (as seen in the right bottom plot) correspond to those observed on the scope (1,2,5,10,15,19 MHz)
    ERL BPM Fscan.gif

December 2006

December 01, 2006 (E. Tanke): ERL BPM status

  • The 4 ADC boards have been mounted into a new BPM box (card list in CESR BPM inventory under ERLBPM/001)
  • The serial#6 processor board is being used, as with the serial#8 one channels 6 and 7 ere not accessible
  • Channel 4 has a large pedestal value (J.Dobbins will follow up on this)

December 06, 2006 (E. Tanke): ERL BPM status

  • Charlie found a bug in the Xilinx code re wait states; has now reverted back to an older version of the Xilinx code
  • John fixed the large pedestal and accessibility problem (1-Dec-2006 entry). The 5 V wasn't properly connected to the VGA on the ADC board; this has been fixed now. New response curves can be found in this EXCEL file.
Topic revision: r4 - 15 May 2007, EugeneTanke
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