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"R&D Towards a Long Shaping-Time Silicon Strip Central Tracker"

The goal of the long shaping-time silicon sensor readout project is to develop readout and data-handling architecture optimized for an ILC detector. Although motivated by an interest in reading out long silicon sensor ladders (to minimize the complexity and material burden of the readout electronics), this R&D is also applicable to the readout of short modules. All current detector concepts include a substantial area of silicon strip detectors; thus, this R&D is globally applicable to Linear Collider detector R&D. Although our group's nominal affiliation is with the SiD concept study, we also consider ourselves contributors to the GLD and LDC efforts, and are lead participants in the SiLC group.

The Santa Cruz Institute for Particle Physics (SCIPP) hardware effort on silicon microstrip readout began with the creation of a detailed simulation of the development, amplification, and digitization of signal pulses induced by incident charged particles. This simulation guided the choice of several aspects of the readout chip design. In particular, the simulation indicated that efficient readout with low occupancy for a 167 cm ladder (one-half the length of the outermost layer of the baseline SiD tracker) could be achieved with a 3 microsecond shaping time. Chosen for the prototype ASIC, this shaping time would also permit timing to within a few crossings of the LC beams, more than adequate for the expected occupancy levels.

The simulation also suggests that, given the extent of fluctuations in the deposited energy, no information would be lost by using the essentially logarithmic time-over-comparator-threshold response to estimate analog pulse heights. However, in order to avoid losing neighboring channel information, a second, lower-threshold comparator needs to be applied to channels neighboring a channel whose pulse-height excites the nominal comparator, whose higher threshold it set to limit noise occupancy. This dual-comparator strategy allows for better than 7 micron resolution for 167 cm ladders (see Figure). It is important to note that, should the SiD design incorporate short, tile-like ladders, this resolution would improve substantially.

The dual-comparator "LSTFE2" front-end ASIC is currently undergoing testing at SCIPP. The amplifier output in mV in response to a calibration step in shown in a second figure (1 MIP is corresponds to about a 3.5 mV step). As designed, the response quickly saturates into its time-over-threshold response; such a high gain is chosen to avoid the effect of process variations on the application of the threshold to sub-MIP signals, which can degrade the effective noise performance of the chip for a multi-channel system.

The SCIPP group has also developed a back-end strategy for buffering and reading out the comparator output. Leading and trailing edges are stored for all high-comparator transitions, as well as low-comparator transitions that are sufficiently close in time and space to high-comparator transitions. The simulation has suggested that a 400 nsec readout clock (roughly 10% of the shaping time) is adequate to preserve time-over threshold information. We have tested this strategy in a simulation of the innermost layer, for a conservative (high) rate of noise and background-hit occupancy, as a function of the low-comparator threshold. The result of this study is shown in the third figure. The predicted data rate of less than 10 kbit per LC machine spill per 128 channel chip scales up to an overall data rate of less than 0.5 GHz to be transmitted off the detector through optical fiber (this would increase by roughly a factor of 10 for short strips), which is a very modest data rate.

SCIPP continues to test the prototype LSTFE2 chip, and is working towards a additional submissions of refined LSTFE designs that will further optimize noise performance as well as expand the channel multiplicity from eight to 128 channels. Within the next year, we hope to have this refined and expanded ASIC under testing at SCIPP, to have verified our digital architecture scheme, and to have explored the properties of the existing LSTFE2 chip on a 1-2 meter long silicon sensor assembly, confirming signal-to-noise projections and timing resolution.

We hope to use the LSTFE chip in a testbeam run in late 2007 or early 2008. In this testbeam run, we will need to demonstrate the power-cycling capabilities of the ASIC, measure efficiency and space-point resolution as a function of incidence angle, and verify the back-end architecture in a realistic environment. While we plan at this point to still have the back-end architecture implemented on an FPGA, incorporation of this digital logic onto the amplifier/comparator ASIC should be relatively straightforward.

Although supported with approximately $50,000 per year of DOE LCRD funding, and some support from the SCIPP base DOE grant, we believe that we will need an augmentation of funds to carry this work out. Design and fabrication of one or two additional prototype ASIC's, and the preparation for and execution of a testbeam run, is only partially covered by existing funding levels. We will need some additional staff, student, equipment, and travel support to be assured of success.
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  • What are the goals of this R&D project. How does this R&D project address the needs of one or more of the detector concepts?

  • If there are multiple institutions participating in this project, please describe the distribution of responsibilities.

  • Are there significant recent results?

  • What are the plans for the near future(about 1 year)? What are the plans on a time scale of 2 to 3 years?

  • Are there critical items that must be addressed before significant results can be obtained from this project?

  • Is the support for this project sufficient? Are there significant improvements that could be made with additional support?