CBETA Instrumentation

Beam Position Monitor System

Diagram of Frequencies

• CBETA_Frequencies.pdf (J. Dobbins, 04/02/2019)

Bunch Pattern Generator

• Block diagram, J. Dobbins, R. Michnoff (CBETA-bunch-pattern-generator-2.pptx, 02/05/2019)
• CBETA-Bunch-Pattern-Generator-U12-Modification-B.pptx, 05/01/2019
• Bunch pattern generator output signals (in0-in3 were converted to outputs)
  • out 0 = pattern clock
  • out 1 = chopper trigger
  • out 2 = inject start clock (no delay)
  • out 3 = laser trigger (limited)
  • in 0 = bpm trigger (configured as output)
  • in 1 = trigger 3 (configured as output)
  • in 2 = trigger 4 (configured as output)
  • in 3 = trigger 5 (configured as output)
  • ext trig 1 = interlock input (logic hi = laser trigger enable)
  • ext trig 2 = fixed logic hi output

• Bunch Pattern Generator Firmware Project Files (Xilinx Vivado 2016.2) located at /nfs/cbeta/bpm/xilinx/projects/v301_pattgen__rev010_6.zip

Bunch Arrival Monitors

• How the BAMs in the splitters might work, Bartnik (BAMs.pptx)
• Master oscillator for BAMs, J. Dobbins (CBETA_Master_Oscillator.pptx, 11/07/2018)
• Fequency of mixer output for for both 1300 MHZ and 2600 MHz is 20.97 MHz (41.935 MHz / 2)
  • For the fractional arc test, the BAM mixer frequency was 12.5 MHz (50 MHz / 4)
• BAM Schematic (BAM_chassis.pdf)
• BAM specs and related schematics
  • ERL_BPM_Top_Schematic.pdf
  • erl_bpm_mixer_schematic.pdf
  • ECA2600P20DA30A-Cornell(181022).pdf
  • ECA1300P20BA30A-Cornell(181022).pdf
  • FN-3708.pdf
  • 7108-306.pdf
  • erl_bpm_IF_filter_response.pdf

Beam Position Monitors

• Beam-Position-Monitors

• BPM Installation spreadsheet for FFA Loop (BPM-cable-list-15.xlsx, 10/15/2019)
  
  • This spreadsheet includes V301 installation information (rack, VME chassis, IP addresses, etc) and will eventually also include cable installation detail
• Ugly hand drawing of BPM cable connections (IMG_1671.jpg)

• BPM cable measurements and matching (CBETA-cable-measurements-2.xlsx, 01/24/2019)
• FFA Rack layout and BPM girder assignments (2019-Full-Loop-level 1-Racks-Equip-Markup.pdf, 10/31/2018)
• BPM non-linear correction comparison (CBETA-BPM-nonlinear-correction-comparison.pptx)
• Directory/filename to start css: /nfs/erl/online/epics/css/CSS_4.1.0/css4.sh
• V301 /operations directory is mounted to /nfs/cbeta/bpm
• To login to one of the V301 modules enter the following command (this example is to log onto erpxbpm01):
  • ssh root@erpxbpm01
• To reboot erpxbpm01 from lnx201, execute the following command:
  • ssh root@erpxbpm01 /sbin/reboot
• Splitter 1 BPM button-to-button measurements
  • Splitter-BPM-Measurement-Jan2018.xlsx
• BPM errors and calibration plan (October 2017)
  • CBETA-BPM-errors-and-calibration-plan-1.docx

• The V301 BPM ADC clock is planned to be:

  • 41.935 * 38 = 1593.5 MHz / 4 = 398.387 MHz

  • With bunches injected every 41.935 MHz, this allows ADC timing to every other bunch

• BPM (V301) Firmware Project Files (Xilinx Vivado 2016.2) located at /nfs/cbeta/bpm/xilinx/projects/v301_bpm__rev613_F.zip

• BPM-AFE-Modifications
• CBETA_clock_trigger_fanout.pptx
  • scau042.pdf (CDCLVC1112 Evaluation Module)
  • cdclvc1112.pdf (CDCLVC1112 specificiation)
• Clock & trigger LVTTL to LVDS RJ45 fanout board
  • trigger_fabout.pdf
  • sn65lvds105.pdf specification

Fast Shutdown System

• fsd_fan-in_schematic.pdf
• FSD_Fan-in_Assembly.pdf
• FSD_Chassis_Inside.jpg
• FSD_Fan-In_Fron_Panel.jpg
• microZed.jpg
• System Documentation (T. Tang, 4/8/2020) FastShutdowndoc-04-08-2020.docx FastShutdowndoc-04-08-2020.pdf
• System Presentation (T. Tang, 4/8/2020) FastShutdownSystem-04-07-20.pptx

IP Address:

• 172.18.45.01. erpzed01.classe.cornell.edu 02:CB:EA:70:10:01
• 172.18.45.02. erpzed02.classe.cornell.edu 02:CB:EA:70:10:02
• 172.18.45.03. erpzed03.classe.cornell.edu 02:CB:EA:70:10:03

Fast Loss Monitor System

• rp_expansion_assembly.pdf
• rp_expansion_schematic.pdf
• RP_to_Front_Panel.pdf
• PMT_BLM_Chassis_Front.jpg
• Red_Pitaya.jpg
• Red_Pitaya_Expansion_Board.jpg
• Red Pitaya ADC spec, LTC2145CUP -14 (21454314fa.pdf), 6 clock pipeline delay
• System Documentation (J. Renta, 4/28/2020), CBETA_FBLM_Documentation_v2.pdf, CBETA_FBLM_Documentation_v2.docx
  
• System Presentation (J. Renta, 4/8/2020), FBLM-Presentation-04-07-2020.pptx
• Firmware
• Software, Readme.txt

Notes from meeting on 4/8/2020 (Rob MIchnoff), 30 attendees:

• Need to consider how to calibrate the ADC measurements to radation with varying PMT voltage settings
  • Can a radiation source in the lab be used or does this need to be done with beam
• Installation of a test led at the end of each fiber could be helpful for system testing
• Some type of watchdog on the output would be beneficial in case the gate array code stops operating when the output is in a high NORMAL state
  • This could be done with an external one-shot that requires a periodic edge issued by the gate array code. Then if the gate array code stops the level would drop to the FAIL state
• The PMT recovery time needs to be understood.
  • If the PMT saturates, what is the time constant to return to zero and allow detection of a new loss signal.
  • The circuit in the PMT socket could be analyzed
• Regarding total time for detection of losses and inhibiting beam, the ADC pipeline delay should be considered
  • A full end-to-end test should include using a pulse on the input and measuring the time from that pulse edge to the output of the FBLM chassis and through the FSD chassis.

For now, all units boot from local system. The following steps were followed to complete this installation:

• Log into lnx201.classe.cornell.edu (or other machine)
• cd /nfs/cbeta/bpm/scripts
• Repeat the following for all units (erpred11 shown here for example)
  • scp init2rp.sh root@erpred11:/etc
  • scp initrp.epics root@erpred11:/etc
  • scp rc.local root@erpred11:/etc
  • ssh root@erpred11 mkdir /firmware (this is where the firmware will be located)
  • scp -p /nfs/cbeta/bpm/fblm/FastBLM_v13.bit root@erpred11:/firmware
  • scp -p /nfs/cbeta/bpm/fblm/fblm root@erpred11:/EPICS/base-3.14.12.5/fblm/bin/linux-arm
  • scp -p /nfs/cbeta/bpm/fblm/Data.db root@erpred11:/EPICS/base-3.14.12.5/fblm/db
• Log into each unit one at a time and perform the following
  • vi /EPICS/base-3.14.12.5/fblm/iocBoot/iocfblm/envPaths
    • change FBLMNAME to correct IOC name for each unit (reference spreadsheet FBLM-IP-addresses-02.xlsx for IOC names, ie IFAFLM0102)
  • vi /etc/initrp.epics
    • change FBLMNAME to correct IOC name for each unit (reference spreadsheet FBLM-IP-addresses-02.xlsx for IOC names, ie IFAFLM0102)
  • make instance directory (IFAFLM0102 shown here for example)
    • mkdir /EPICS/instances/IFAFLM0102
    • mkdir /EPICS/instances/IFAFLM0102/autosave
• AUTOSAVE/RESTORE FEATURE
  • Steps taken to get the autosave feature working from within a redpitaya, for example: root@erpred11
    
    • scp -p cbetabpm@lnx201.classe.cornell.edu:/nfs/cbeta/bpm/fblm/SourceCode/st.cmd /EPICS/base-3.14.12.5/fblm/iocBoot/iocfblm
    • scp -p cbetabpm@lnx201.classe.cornell.edu:/nfs/cbeta/bpm/fblm/SourceCode/asList.req /EPICS/base-3.14.12.5/fblm/iocBoot/iocfblm/autosave
      • Initially, asList.req was a directory, remove it, then try to scp the asList.req file again:
        • rmdir /EPICS/base-3.14.12.5/fblm/iocBoot/iocfblm/autosave/asList.req
    • Refer to steps in this image to verify that the autosave feature works (Remember that a reboot is needed to verify)
    • Repeat for all redpitayas

Beam Loss Monitor System

• Fast BLM chassis IP and MAC addresses (FBLM-IP-addresses-02.xlsx)
• Presentation on using scintillating fiber with PMT for loss monitor (pptx, T. Miller)

Master Oscillator

• Master Oscillator drawings:
  • _{The page called CESR_ERL_SYNTHESIZER - ASSEMBLY.pdf is the top level drawing. The block labelled EVM contains Texas Instruments CDC7005 Evaluation Board. The block labelled ADPLL contains a Cornell designed board hosting two Analog Device ADF4106 PLL ICs, detail in sheet labelled CESR_ERL SYNTHESIZER - ADPLL.pdf The CDC7005 and ADF4106 each have programmable registers. These two devices do the important work.}
  • CESR_ERL SYNTHESIZER -OCXO BUFFER.pdf
  • CESR_ERL SYNTHESIZER - CLOCK DISTRIBUTOR.pdf
  • CESR_ERL SYNTHESIZER CONTROLLER.pdf
  • CESR_ERL SYNTHESIZER - ASSEMBLY.pdf
  • CESR_ERL SYNTHESIZER - LOW NOISE REGULATOR.pdf
  • CESR_ERL SYNTHESIZER - ADPLL.pdf
  • CESR_ERL SYNTHESIZER - ADPLL (2).pdf
• HZB_synthesizer.pdf

Notes

• Instrumentation tasks: https://docs.google.com/document/d/1tlKHo-BvtAtblwKl31XCGAoTQ2Mm0zSR9EhcQgrxoww/edit
• ... and related system details: https://docs.google.com/document/d/17zMmvpx_o7KKpWnyjVkcex6zkIs_OlP0kqpgnpAfcVg/edit

caBPMs.pl

• The perl script, caBpms.pl can be executed as erpopr and is used to write or read a V301 BPM record value for all BPM modules in the specified list. For example:
  • caBpms.pl -a attenA1S (read value for attenA1S for all CBETA V301 BPMs)
  • caBPMs.pl -fa attenA1S 31 (write 31 to all CBETA V301 BPMs in permanent magnet girder section FA)
• Valid dash arguments include:
  • -a (all), -s1 (s1), -fa (fa), -1 (all in vme chassis 01), -2 (all in vme chassis 02), -3, -4, .. -12
• The executable is in /home/erpopr/bin and the planelist files are in /home/michnoff/scripts/BPM/planelists

initBpms and init1Bpm

• The scripts initBpms and init1Bpm are used to initlize a set of the BPM IOC records to reasonable values.
  • init1Bpm takes one argument that is the epics name (IFABPM01, IS1BPM01, etc.)
  • initBpms takes one argument to identify which group of BPMs is configured. This script consists of a series of calls to caBpms.pl, one for each of the records that is initialized. The argument is the same as the dash argument used for caBPMs.pl.
• The execuatable are located in /home/erpopr/bin and the planelist files are in /home/michnoff/scripts/BPM/planelists

EPICS

• edm should be executed as erpopr. To login as erpopr enter the following:
  • ssh -X erpopr@erp201
• Directory for edm: /nfs/erl/online/epics; Filename to start epics screens: ./l0_screens.sh (letter L, zero)

-- RobMichnoff - 28 Mar 2017